Area-Optimized Technology Mapping for Hybrid FPGAs

As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation has introduced a new family of LUT-based FPGAs that have been augmented with userconfigurable programmable logic array blocks (PLAs). In this paper a novel FPGA technology mapping approach is described that automatically partitions user designs into netlist subgraphs appropriately-sized for implementation on both types of available user resources. The subgraphs are subsequently mapped to assigned target resources. It is shown that fast estimation of post-minimization product term counts plays an especially important role in the mapping of designs to PLAs.